This invention relates to switched-capacitor power converters, and particularly to systems and methods for reducing power loss therein.
Power converters are widely used in a range of electronic and electro-mechanical systems to efficiently process and deliver energy where the energy source may supply power at one voltage level and the load requires a substantially different voltage level. Efficient power converters use switching techniques and energy storage components such as capacitors or inductors to transform voltage and current levels to the levels required by the load. For example, a microprocessor may operate at 1 V and 100 A, but the system power bus or battery provides a 12 V supply. A power converter, in this case a DC-DC converter, is needed to transform the 12 V supply to a 1 V supply that can be used by the microprocessor.
Switched-capacitor (SC) DC-DC converters have gained prominence in recent years due to several favorable characteristics. One advantage of SC converters is that they provide better utilization of semiconductor switching devices (such as MOSFETS) compared to inductor-based topologies (such as buck or boost converters). This is especially true in situations where the ratio of the supply voltage to the required output voltage (also known as the conversion ratio) is high. Specifically, the advantage of SC topologies is the ability to operate with lower conduction loss (power loss that occurs due to the flow of electrical current) for a given voltage-current (V-A) current rating of the power devices.
Additional trends that favor SC converters are the inherently higher energy-density (defined as the maximum energy storage a component can achieve divided by the component's area or volume) of capacitors compared to inductors in many voltage and current ranges. The energy-density of capacitors that can be integrated in integrated circuits using semiconductor microfabrication techniques is considerably higher than can be achieved using integrated inductors and other magnetic components. Also, new microfabrication techniques have enabled much higher energy density compared to what was available in traditional semiconductor processes.
A primary source of energy loss in switched-capacitor converters is ‘bottom-plate’ switching loss that is associated with the bottom-plate parasitic capacitance of the switched capacitor energy storage element. The ‘bottom-plate’ can be characterized by parasitic capacitance that is reference to a fixed common voltage (for example to ground).
FIG. 1 depicts an exemplary prior art 2:1 switched-capacitor converter 100. Switched-capacitor converter 100 includes a supply (Vin) 102, a load determined based on Vout 104 and Iout 106, a plurality of bypass capacitances (Cbypass) 108, a flying capacitance (Cx) 110, and a bottom-plate parasitic capacitance (Cbp) 116. The bottom-plate parasitic capacitance is shown in FIG. 1 for a 2:1 switched capacitor converter. Supply/Vin 102 represents the power supply or energy source. Iout 106 represents the load current with power delivered to the load being the product of Vout 104 times Iout 106. Cbypass 108(1) represents bypass capacitance that is used to filter the input and output voltage levels (it should be noted that bypass capacitance is not needed in all cases, for example, the architecture reported in H. Le, S. R. Sanders, E. Alon, “Design Techniques for Fully Integrated Switched-Capacitor DC-DC converters,” IEEE J. Solid-State Circuits, 2011, vol. 46, no. 9, pp. 2120-2131. Cx 110 represents the switched capacitance or flying capacitance that is used to move energy from the supply to the load, Cbp 116 represents the bottom-plate parasitic capacitance of the flying capacitance. Cbp 116 can represent parasitic capacitance of either terminal of Cx 110 to any substantially constant (common) voltage, but it is most common that the ‘bottom’ plate of the Cx 110 is physically closer to a ground-plane or a semiconductor substrate, which is why it is referred to as the “bottom-plate.”
FIG. 2 depicts an exemplary prior art physical representation 200 of a flying capacitor Cx 110, of FIG. 1. FIG. 2 illustrates Cx 110, of FIG. 1 characterized as two parallel conductors (i.e. top plate 202 and bottom-plate 204) separated by a dielectric 206. The parasitic capacitances Cbp 116 and Ctp 216 are shown as the capacitance between either of the plates 202, 204 and a common voltage plane 210 that may be the substrate of a semiconductor chip, or a fixed voltage plane such as a ground plane. As the bottom-plate 204 is typically closer to the semiconductor substrate in integrated-circuit implementations, Cbp 116 tends to be the dominant parasitic. However, Ctp 216 may also be an important loss mechanism, and the loss mitigation strategy described herein applies equally to Cbp 116 and Ctp 216, as these can typically be lumped into a single common-mode capacitance.
Switched-capacitor converters operate by reconfiguring (or switching) the configuration of the flying capacitor with respect to different voltage nodes in the system. For example, in the 2:1 converter shown in FIG. 1, in phase 1, Cx 110 is connected in parallel with Vin 102 and Vout 104 through MOSFET switches 112(2), 112(4) that are controlled by voltages VB and VD, respectively. In phase 1, MOSFET switches 112(1), 112(3), controlled by voltages VA and VC, respectively, are substantially ‘off’ or in high impedance mode. During this time, charge flows into Cx 110 such that it stores energy substantially equal to:
                              E                                    C              x                        -                          φ              1                                      =                              1            2                    ⁢                                                    C                x                            ⁡                              (                                                      V                                          i                      ⁢                                                                                          ⁢                      n                                                        -                                      V                    out                                                  )                                      2                                              Equation        ⁢                                  [        1        ]            
In phase 2, Cx 110 is reconfigured to be in parallel with Vout and GND 114. At the end of phase 2, Cx 110 is storing energy according to:
                              E                                    C              x                        -                          φ              1                                      =                              1            2                    ⁢                                                    C                x                            ⁡                              (                                                      V                    out                                    -                  GND                                )                                      2                                              Equation        ⁢                                  [        2        ]            
If there is a voltage difference between quantities (Vin−Vout) and (Vout−GND), net energy will flow in the direction where the voltage difference is lower. For example, if Vout 104 is less than (Vin 102)−(Vout 104), energy will flow to Vout 104.
FIG. 3 depicts a common representation 300 for the SC voltage conversion process. The operation of a SC converter with an N:1 conversion ratio, as depicted in FIG. 3, can be represented as an N:1 transformer with series-connected output resistance, REFF. The transformer captures the efficient voltage and current transformation process, and REFF captures the conduction losses in the system. Analytical expressions for REFF have been derived for different conversion ratios and operating regimes. The simplest expression is derived using the energy balance description discussed above. In this case, REFF=1/(fswCx), where fsw is the switching frequency and Cx is the flying capacitance. This expression is accurate for switching frequencies where the reactance of the flying capacitor is the dominant impedance in the circuit. This has been described as the “slow-switching limit.” As switching frequency increases, the energy transferred into the flying capacitor in each phase may be limited by either ‘effective series resistance’ (ESR), or ‘effective series inductance’ (ESL). ESR or RESR results from parasitic resistance of capacitors, metal interconnect, and semiconductor switches. ESL results from parasitic inductance in the loop containing flying capacitor(s), bypass capacitor(s), interconnect, and switches.
FIG. 4 is a prior-art graph depicting effective resistance normalized to effective series resistance versus frequency for switched-capacitor and resonant switched-capacitor (ReSC) converters. FIG. 4 depicts the normalized quantity REFF/RESR for a 2:1 switched capacitor converter (does not include ESL). At low frequencies the converter operates in the SSL mode. At high frequencies, the minimum achievable REFF is limited by RESR. It is important to minimize REFF to also minimize power loss (maximize efficiency and minimize conduction losses), and so that Vout is substantially equal to Vin/N. However, it can be seen that to minimize REFF, the SC circuit must switch faster. This causes increasing switching losses, or losses that are proportional to switching frequency. Switching losses include power loss required to switch the power semiconductor devices and also any frequency dependent losses from reconfiguring the flying capacitor, such as bottom-plate switching loss.
Bottom-plate switching losses occur due to losses in switching the bottom-plate parasitic capacitance between Vout and GND every switching cycle. For example, using the description above with reference to FIG. 1, Cbp is connected in parallel with Vout, storing energy according to the following:
                              E                                    C                              b                ⁢                                                                  ⁢                p                                      -                          φ              1                                      =                              1            2                    ⁢                                                    C                                  b                  ⁢                                                                          ⁢                  p                                            ⁡                              (                                  V                  out                                )                                      2                                              Equation        ⁢                                  [        3        ]            
In phase 2, the bottom-plate is shorted out with both terminals connected to GND, so that its net energy storage becomes zero. This results in power loss of:PCbp=Cbp(Vout)2fsw  Equation [4]
Bottom-plate parasitic capacitance is usually characterized through “bottom-plate-ratio” which is the ratio of bottom-plate parasitic capacitance to flying capacitance. It has further been shown that for a bottom-plate-ratio of 1%, the maximum achievable efficiency for a 2:1 switched-capacitor converter is 90.9%.
FIG. 5A depicts a prior art charge recycling system 500 for a multi-phase switched-capacitor converter. Within system 500, a first switched capacitor sub-converter 502 and second switched capacitor sub-converter 504 operate at 180 degrees out of phase. Each of the switched capacitor sub-converter 502, 504 include a first transistor 506(1), 508(1) a second transistor 506(2), 508(2) a third transistor 506(3), 508(3) and a fourth transistor 506(4), 508(4). Within first switched capacitor sub-converter 502, first transistor 506(1) has a source connected to Vin and a gate connected to a first clock signal (clk1) 510(1), and a drain connected to a drain of second transistor 506(2). The gate of second transistor 506(2) is connected to a second clock signal (clk2) 510(2), and the source of second transistor 506(2) is connected to the source of third transistor 506(3). The gate of third transistor 506(3) is connected to a third clock signal (clk3) 510(3), and the source of third transistor 506(3) is connected to the source of fourth transistor 506(4). The gate of fourth transistor 506(4) is connected to a fourth clock signal (clk4) 510(4), and the drain of fourth transistor 506(4) is connected to ground (GND). In the embodiment shown within FIG. 5, the first and third transistors, 506(1), 506(3) are p-channel MOSFETS, and the second and fourth transistors 506(2), 506(4) are n-channel MOSFETS. First switched capacitor sub-converter 502 further includes a flying capacitor (C) 518 connected to the drain of first transistor 506(1) and the drain of third transistor 506(3). First switched capacitor sub-converter 502 further includes bottom-plate parasitic capacitance (Cbp1) 514 connected between ground and the drain of third transistor 506(3).
Within second switched capacitor sub-converter 504, first transistor 508(1) has a source connected to Vin and a gate connected to inverted, via an inverter 512, second clock signal (clk2) 510(2), and a drain connected to a drain of second transistor 508(2). The gate of second transistor 508(2) is connected to inverted first clock signal (clk1) 510(1), via an inverter 512, and the source of second transistor 508(2) is connected to the source of third transistor 508(3). The gate of third transistor 508(3) is connected to inverted, via an inverter 512, fourth clock signal (clk4) 510(4), and the source of third transistor 508(3) is connected to the source of fourth transistor 508(4). The gate of fourth transistor 508(4) is connected to inverted, via an inverter 512, third clock signal (clk3) 510(3), and the drain of fourth transistor 508(4) is connected to ground (GND). In the embodiment shown within FIG. 5, the first and third transistors, 508(1), 506(3) are p-channel MOSFETS, and the second and fourth transistors 506(2), 508(4) are n-channel MOSFETS. Second switched capacitor sub-converter 504 further includes a flying capacitor (C) 520 connected to the drain of first transistor 508(1) and the drain of third transistor 508(3). Second switched capacitor sub-converter 504 further includes a bottom-plate parasitic capacitance (Cbp1) 516 connected between ground and the drain of third transistor 508(3)
System 500 utilizes interleaved first and second switched capacitor sub-converters 502, 504. For example two identical SC converters operate 180 degrees out of phase (phase 1 and phase 2 from the above description are reversed for each SC stage). In between phase 1 and phase 2, consider that Cbp1 514 is charged to Vout and Cbp2 516 is charged to 0 V. A switch (Scr) 522 is turned on to share the bottom-plate charge from Cbp1 514 to Cbp2 516. If these capacitors are equal in magnitude, then after the end of the charge recycling phase, the voltage on Cbp1=Cbp2˜Vout/2. Then in the next phase Cbp2 516 only needs to be charged from Vout/2 to Vout, which reduces bottom-plate loss by up to 50%. While this is a valuable approach, it is limited by only recovering 50% of the bottom-plate power loss.
FIG. 5B illustrates an exemplary gate driver circuit 550 for generating signals clk1 through clk4 in order to drive the charge recycling system 500, of FIG. 5A. Gate driver circuit 550 operates for example as described in FIG. 6 of T. M. Anderson, F. Krismer and J. W. Kolar “A 4.6 W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS”, Proceedings of the International Solid-State Circuits Conference (ISSCC 2013), San Francisco, USA, Feb. 17-21, 2013.
FIG. 6 depicts a timing diagram 600 of signal waveforms for the charge sharing schematic of FIG. 5. Here clk3 and clk4 transition between GND and Vout. Signals clk1 and clk2 (not shown) would be synchronized with clk3 and clk4 respectively but would transition between VDD and Vout. When clk3 is high and clk4 is low, all switches are “off” and in a high impedance state. At this time, clkcr transitions high, connecting Cbp1 and Cbp2. Charge is transferred between these capacitors as indicated by the voltages across them (Vcb1 and Vcp2 respectively). Then when clk3 transitions low, the amount of charge needed to charge Cbp1 to Vout is (Vout/2)·Cbp1, which reduces power loss by roughly ½ in ideal circumstances.
The above described multi-phase switched-capacitor converters lack in efficiency. For example, there is still appreciable loss to the bottom-plate parasitic capacitance elements as the prior art charge recycling scheme is limited to only recovering 50 percent of the bottom-plate power loss.